at29lv010a 1 megabit (128k x 8) 3-volt only cmos flash features single supply voltage, range 3v to 3.6v 3-volt-only read and write operation software protected programming fast read access time - 150 ns low power dissipation 15 ma active current 20 m a cmos standby current sector program operation single cycle reprogram (erase and program) 1024 sectors (128 bytes/sector) internal address and data latches for 128-bytes two 8 kb boot blocks with lockout fast sector program cycle time - 20 ms internal program control and timer data polling for end of program detection typical endurance > 10,000 cycles cmos and ttl compatible inputs and outputs commercial and industrial temperature ranges description the at29lv010a is a 3-volt-only in-system flash programmable and erasable read only memory (flash). its 1 megabit of memory is organized as 131,072 bytes by 8 bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 150 ns with power dissipation of just 54 mw over the commercial temperature range. when the device is deselected, the cmos standby current is less than 20 m a. the device endurance is such that any sector can typically be written to in excess of 10,000 times. to allow for simple in-system reprogrammability, the at29lv010a does not require high input voltages for programming. three-volt-only commands determine the opera- tion of the device. reading data out of the device is similar to reading from an eprom. reprogramming the at29lv010a is performed on a sector basis; 128-bytes of data are loaded into the device and then simultaneously programmed. (continued) pin configurations pin name function a0 - a16 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect tsop top view type 1 plcc top view 0520b at29lv010a 4-53
(continued) block diagram during a reprogram cycle, the address locations and 128- bytes of data are captured at microprocessor speed and internally latched, freeing the address and data bus for other operations. following the initiation of a program cy- cle, the device will automatically erase the sector and then program the latched data using an internal control timer. the end of a program cycle can be detected by data poll- ing of i/o7. once the end of a program cycle has been detected, a new access for a read or program can begin. description (continued) device operation read: the at29lv010a is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual- line control gives designers flexibility in preventing bus contention. software data protection programming: the at29lv010a has 1024 individual sectors, each 128- bytes. using the software data protection feature, byte loads are used to enter the 128-bytes of a sector to be programmed. the at29lv010a can only be programmed or reprogrammed using the software data protection fea- ture. the device is programmed on a sector basis. if a byte of data within the sector is to be changed, data for the en- tire 128-byte sector must be loaded into the device. the data in any byte that is not loaded during the programming of its sector will be indeterminate. the at29lv010a auto- matically does a sector erase prior to loading the data into the sector. an erase command is not required. software data protection protects the device from inadver- tent programming. a series of three program commands to specific addresses with specific data must be presented to the device before programming may occur. the same three program commands must begin each program op- eration. all software program commands must obey the sector program timing specifications. power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent pro- gram cycles during power transitions. any attempt to write to the device without the 3-byte com- mand sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , a read operation will effectively be a polling operation. after the software data protections 3-byte command code is given, a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. the 128-bytes of data must be loaded into each sector. any byte that is not loaded during the programming of its sector will be erased to read ffh. once the bytes of a sec- tor are loaded into the device, they are simultaneously programmed during the internal programming period. af- ter the first data byte has been loaded into the device, suc- cessive bytes are entered in the same manner. each new byte to be programmed must have its high to low transition on we (or ce) within 150 m s of the low to high transition of we (or ce) of the preceding byte. if a high to low transition is not detected within 150 m s of the last low to high transi- tion, the load period will end and the internal programming period will start. a7 to a16 specify the sector address. the sector address must be valid during each high to low tran- sition of we (or ce). a0 to a6 specify the byte address within the sector. the bytes may be loaded in any order; sequential loading is not required. once a programming operation has been initiated, and for the duration of t wc , a read operation will effectively be a polling operation. 4-54 at29lv010a
(continued) hardware data protection: hardware features protect against inadvertent programs to the at29lv010a in the following ways: (a) v cc sense if v cc is below 1.8v (typical), the program function is inhibited. (b) v cc power on delay once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) be- fore programming. (c) program inhibit holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. input levels: while operating with a 3.3v 0.3v power supply, the address inputs and control inputs ( oe, ce and we) may be driven from 0 to 5.5v without ad- versely affecting the operation of the device. the i/o lines can be driven from 0 to v cc + 0.6v . product identification: the product identifica- tion mode identifies the device and manufacturer as at- mel. it may be accessed by hardware or software opera- tion. the hardware operation mode can be used by an ex- ternal programmer to identify the correct programming al- gorithm for the atmel product. in addition, users may wish to use the software product identification mode to identify the part (i.e. using the device code), and have the system software use the appropriate sector size for program op- erations. in this manner, the user can have a common board design for 256k to 4-megabit densities and, with each densitys sector size in a memory map, have the sys- tem software apply the appropriate sector size. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the at29lv010a features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. device operation (continued) temperature under bias................. -55c to +125c storage temperature...................... -65c to +150c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on a9 (including nc pins) with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data p o l l i n g t h e at29lv010a provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. optional chip erase mode: the entire device can be erased by using a 6-byte software code. please see software chip erase application note for details. boot block programming lockout: the at29lv010a has two designated memory blocks that have a programming lockout feature. this feature pre- vents programming of data in the designated block once the feature has been enabled. each of these blocks con- sists of 8k bytes; the programming lockout feature can be set independently for either block. while the lockout fea- ture does not have to be activated, it can be activated for either or both blocks. these two 8k memory sections are referred to as boot blocks . secure code which will bring up a system can be contained in a boot block. the at29lv010a blocks are located in the first 8k bytes of memory and the last 8k bytes of memory. the boot block programming lockout feature can therefore support systems that boot from the lower addresses of memory or the higher addresses. once the programming lockout feature has been acti- vated, the data in that block can no longer be erased or programmed; data in other memory locations can still be changed through the regular programming methods. to activate the lockout feature, a series of seven program commands to specific addresses with specific data must be performed. please see boot block lockout feature en- able algorithm. if the boot block lockout feature has been activated on either block, the chip erase function will be disabled. at29lv010a 4-55
1. after power is applied and v cc is at the minimum specified data sheet value, the system should wait 20 ms before an operational mode is started. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 1 m a i lo output leakage current v i/o = 0v to v cc 1 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc com. 20 m a ind. 50 m a i sb2 v cc standby current ttl ce = 2.0v to v cc 1ma i cc v cc active current f = 5 mhz; i out = 0 ma; v cc = 3.6v 15 ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma; v cc = 3.0v .45 v v oh output high voltage i oh = -100 m a; v cc = 3.0v 2.4 v dc and ac operating range at29lv010a-15 at29lv010a-20 AT29LV010A-25 operating temperature (case) com. 0c - 70c 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c -40c - 85c v cc power supply (1) 3.3v 0.3v 3.3v 0.3v 3.3v 0.3v operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in 5v chip erase v il v ih v il ai standby/write inhibit v ih x (1) x x high z program inhibit x x v ih program inhibit x v il x output disable x v ih x high z product identification hardware v il v il v ih a1 - a16 = v il , a9 = v h , (3) a0 = v il manufacturer code (4) a1 - a16 = v il , a9 = v h , (3) a0 = v ih device code (4) software (5) a0 = v il , a1 - a16 =v il manufacturer code (4) a0 = v ih , a1 - a16 =v il device code (4) 4. manufacturer code: 1f, device code: 35. 5. see details under software product identification entry/exit. notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. boot block lockout detection: a software method is available to determine whether programming of either boot block section is locked out. see software prod- uct identification entry and exit sections. when the device is in the software product identification mode, a read from location 00002h will show if programming the lower ad- device operation (continued) dress boot block is locked out while reading location 1fff2h will do so for the upper boot block. if the data is fe, the corresponding block can be programmed; if the data is ff, the program lockout feature has been activated and the corresponding block cannot be programmed. the software product identification exit mode should be used to return to standard operation. 4-56 at29lv010a
ac read characteristics at29lv010a-15 at29lv010a-20 AT29LV010A-25 symbol parameter min max min max min max units t acc address to output delay 150 200 250 ns t ce (1) ce to output delay 150 200 250 ns t oe (2) oe to output delay 0 100 0 100 0 120 ns t df (3, 4) ce or oe to output float 0 50 0 50 0 60 ns t oh output hold from oe, ce or address, whichever occurred first 000ns t r , t f < 5 ns input test waveforms and measurement level output test load pin capacitance (f = 1 mhz, t = 25c) (1) typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v note: 1. these parameters are characterized and not 100% tested. notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) at29lv010a 4-57
ce controlled ac byte load characteristics symbol parameter min max units t as , t oes address, oe set-up time 10 ns t ah address hold time 100 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 200 ns t ds data set-up time 100 ns t dh , t oeh data, oe hold time 10 ns t wph write pulse width high 200 ns ac byte load waveforms (1, 2) we controlled 4-58 at29lv010a
3. all bytes that are not loaded within the sector being programmed will be indeterminate. program cycle characteristics symbol parameter min max units t wc write cycle time 20 ms t as address set-up time 10 ns t ah address hold time 100 ns t ds data set-up time 100 ns t dh data hold time 10 ns t wp write pulse width 200 ns t blc byte load cycle time 150 m s t wph write pulse width high 200 ns load data to sector (128 bytes) (3) load data a0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 notes for software program code: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. data protect state will be re-activated at end of program cycle. 3. 128-bytes of data must be loaded. enter data protect state (2) writes enabled programming algorithm (1) software protected program waveform notes: 1. oe must be high when we and ce are both low. 2. a7 through a16 must specify the sector address during each high to low transition of we (or ce) after the software code has been entered. at29lv010a 4-59
toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1, 3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling waveforms 4-60 at29lv010a
pause 20 ms load data 90 to address 5555 load data 55 to address 2aaa load data aa to address 5555 notes for software product identification: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a16 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 1f device code: 35 enter product identification mode (2, 3, 5) software product identification entry (1) pause 20 ms load data f0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 exit product identification mode (4) software product identification exit (1) load data 80 to address 5555 load data 55 to address 2aaa boot block lockout feature enable algorithm (1) notes for boot block lockout feature enable: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. lockout feature set on lower address boot block. 3. lockout feature set on higher address boot block. load data aa to address 5555 load data 55 to address 2aaa load data aa to address 5555 pause 20 ms load data ff to address fffffh (3) pause 20 ms load data 00 to address 00000h (2) load data 40 to address 5555 at29lv010a 4-61
ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 150 15 0.02 at29lv010a-15jc 32j commercial at29lv010a-15tc 32t (0 to 70 c) 15 0.05 at29lv010a-15ji 32j industrial at29lv010a-15ti 32t (-40 to 85 c) 200 15 0.02 at29lv010a-20jc 32j commercial at29lv010a-20tc 32t (0 to 70 c) 15 0.05 at29lv010a-20ji 32j industrial at29lv010a-20ti 32t (-40 to 85 c) 250 15 0.02 AT29LV010A-25jc 32j commercial AT29LV010A-25tc 32t (0 to 70 c) 15 0.05 AT29LV010A-25ji 32j industrial AT29LV010A-25ti 32t (-40 to 85 c) package type 32j 32 lead, plastic j-leaded chip carrier (plcc) 32t 32 lead, thin small outline package (tsop) 4-62 at29lv010a
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